It is hierarchical netlist that show connectivity. It contains model, port list, template. It can be used to generate read back ascii (RBA) file. RBA contains readback commands and expected readback data.
FPGA Verification Model:
VHDL/Verilog -> Map -> Fit -> Asm -> SOF
-> BCM netlist
logical physical
netlist netlist
Multiplexer (MUX):
A device that selects one of several input signals and sends the selected signal to output line. A multiplexer of of 2n inputs has n select lines, which are used to select which input line to send to the output line.
An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal.
Flip-Flop:
A flip-flop is a circuit capable of two stable states and represents a single bit.
Registers:
A register is a group of flip-flops that stores a bit pattern. A register on the FPGA has a clock, input data, output data, and enable signal port. Every clock cycle, the input data is latched, stored internally, and the output data is updated to match the internally stored data.
Look-Up Table (LUT):
A LUT is a collection of logic gates hard-wired on the FPGA. LUTs store a predefined list of outputs for every combination of inputs and provide a fast way to retrieve the output of a logic operation
Block RAM:
It is block memory, it is RAM that is embedded throughout the FPGA for storing data. The block RAM can be SRAM or memory logic array block (MLAB).
FPGA:
Logic resources are resources on the FPGA that can perform logic functions. Logic resources are grouped in slices to create configurable logic blocks. A slice contains a set number of LUTs, flip-flops and multiplexers. The logic resources can be logic blocks, IO blocks, programmable routing block; they are the building blocks of FPGA.
Functional simulation - before design compilation
Timing simulation - after design compilation
LCB - LAB Control Block
ALE - Aggregate Logic Elements
Combinational Circuit:
Combinational logic circuits implement Boolean functions. Boolean functions are mappings of input bit strings to output bit strings. So, it means that if you feed in an input to a circuit, say, 000, then look at its output, and find that it is, 1, then the output will always be 1 for that circuit, if 000 is the input. Meaning 000 is mapped to 1. Combinational circuit are functions of their inputs, and are NOT based on clocks.
Sequential Circuit:
Unlike combinational logic, sequential circuits have state, which means basically, sequential circuits have memory. The state logic is implemented with flip flops. The main difference between sequential circuits and combinational circuits is that sequential circuits compute their output based on input and state, and that the state is updated based on a clock.
Verilog:
Verilog is case sensitive.
Reg and Wire
reg can store value and drive strength. It can be used for modeling both combinational and sequential circuit.
wire cannot store a value, it can be assigned a value, and used for connecting output port to the actual driver. it is used for making combinational circuit.
reg array:
verilog thinks in bits.
reg [7:0] datain_reg; /* 8x1 bit reg */
reg datain_reg[0:7]; /* An 8-bit reg */
reg [7:0] datain_reg[0:3]; /* 8x4 bit reg */
reg [7:0] datain_reg[0:7]; /* 8x8 bit reg */
wire [7:0] dataout_wire; /* 8x1 bit wire */
Use assign with wire:
assign dataout_wire[0]= 1'b0;
We can compare wire and reg array value:
reg [7:0] datain_reg;
wire [7:0] dataout_reg;
reg result;
if (datain_reg[i] != dataout_wire [i])
begin
result = 1'b0;
end
Always block
always @(a) /*level-trigger*/
always @(posedge a) /*edge-trigger for positive transation*/
valid for the following positive transition.
x -1
0-1
?-1
always @(posedge clk)
begin
q <= d
x<=q
z<=x
end
for non blocking statement, it will execute in sequence, but result is not available immediately.
Blocking and Nonblocking Statements
One can use the nonblocking statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other
module block_nonblock(); reg a, b, c, d , e, f ; // Blocking assignments initial begin a = #10 1'b1;// The simulator assigns 1 to a at time 10 b = #20 1'b0;// The simulator assigns 0 to b at time 30 c = #40 1'b1;// The simulator assigns 1 to c at time 70 end // Nonblocking assignments initial begin d <= #10 1'b1;// The simulator assigns 1 to d at time 10 e <= #20 1'b0;// The simulator assigns 0 to e at time 20 f <= #40 1'b1;// The simulator assigns 1 to f at time 40 end endmodule |
